تگ Cache

جزئیات خدمات ترجمه در ترجمه تخصصی

cache
caching
cache
cache
active queue management
a[i] b[i] c[i]
afheye 805
IEEE COMPUTER ARCHITECTURE LETTERS, VOL. 12, NO. 2, JULY-DECEMBER 2013 59
[3B2-14] mdt2011010044.3d 13/1/011 15:51 Page 44
Journal of Computational Science 5 (2014) 90–98
Journal of Computational Science 5 (2014) 90–98
Journal of Computational Science 5 (2014) 90–98
Settings have been successfully updated Unable to write to file
==================================================
CHECKPOINT -- writes any unwritten buffers.
cache
Adaptive Software Cache Management for
J.ParallelDistrib.Comput.74(2014)3071–3086
The Bw-Tree: A B-tree for New Hardware
J.ParallelDistrib.Comput.74(2014)3071–3086
Intelligently
16th Euromicro Conference on Parallel, Distributed and Network-Based Processing 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing
Deploying Video-on-Demand Services on Cable
and automobile as a paradigm shift in the way people
Hierarchical Placement and Network Design Problems
[3B2-11] mmi2011020086.3d 22/3/011 15:27 Page 86
WEB STANDARDS SOLUTIONS
SPAGNA LAYOUT_Layout 1 4/1/13 1:34 PM Page 132
low power microprocessors designed for Mobile Internet Devices and ultra
In this tutorial we will explore the architecture used on
Leases: An Efficient Fault-Tolerant Mechanism
Leases: An Efficient Fault-Tolerant Mechanism
Leases: An Efficient Fault-Tolerant Mechanism
SEC. 8.1 MULTIPROCESSORS 539
dundancy for L1 caches corresponding to the L2 cache with
.. · ... ·.·.
A Hybrid Cache Replacement Policy for Heterogeneous Multi-Cores
A Hybrid Cache Replacement Policy for Heterogeneous Multi-Cores
A Hybrid Cache Replacement Policy for Heterogeneous Multi-Cores
International Conference on Networking, Architecture, and Storage International Conference on Networking, Architecture, and Storage
Hoseini-Hesam05
Hoseini-Hesam06
1136 IEEE SYSTEMS JOURNAL, VOL. 8, NO. 4, DECEMBER 2014
1136 IEEE SYSTEMS JOURNAL, VOL. 8, NO. 4, DECEMBER 2014
Hoseini-Hesam-San05
Hoseini-Hesam-San06
Lawrence Berkeley National Laboratory
Protecting Browser State from Web Privacy Attacks
Protecting Browser State from Web Privacy Attacks
Protecting Browser State from Web Privacy Attacks
Skinﬂint DRAM System: Minimizing DRAM Chip Writes for Low Power
A Trend Micro Research Paper
1136 IEEE SYSTEMS JOURNAL, VOL. 8, NO. 4, DECEMBER 2014
1136 IEEE SYSTEMS JOURNAL, VOL. 8, NO. 4, DECEMBER 2014
1136 IEEE SYSTEMS JOURNAL, VOL. 8, NO. 4, DECEMBER 2014
Protecting Browser State from Web Privacy Attacks
106
54159
•
Leases: An Efficient Fault-Tolerant Mechanism
The Design and Implementation of Open vSwitch 2 Design Constraints
The Design and Implementation of Open vSwitch
Dead Block Replacement and Bypass with a Sampling Predictor
Instruction-based Reuse Distance Prediction Replacement Policy
CRC: Protected LRU Algorithm
SCORE: A Score-Based Memory Cache Replacement Policy
Cache-aware Named-data Forwarding in Internet of
Cache-aware Named-data Forwarding in Internet of
Downloaded from http://iranpaper.ir
1
Timing Anomalies in Dynamically Scheduled Microprocessors
systems currently generate a major fraction of the total Internet
COMPUTER SCIENCE REVIEW ( ) –
for studying activity recognition in a naturalis-
for studying activity recognition in a naturalis-
4 4
4 4
MODELING AND CACHING OF PEER-TO-PEER
An Oracle server includes an Oracle Instance and an Oracle
2856 IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 60, NO. 5, MAY 2014
MADDAH-ALI AND NIESEN: FUNDAMENTAL LIMITS OF CACHING 2857
2862 IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 60, NO. 5, MAY 2014
Your installation seems to be missing core Kinsta files managing
FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access
U n i t � 2 � � � � � � � � � � � � � � � � C o m p u t e r � A r c h i t e c t u r e s �
Available online at www.sciencedirect.com
Cache Performance Research for Embedded Processors
Cache Performance Research for Embedded Processors
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LCA.2017.2701370, IEEE Computer
Thi T T T Th T T T Th Th
Your installation seems to be missing core Kinsta files managing
st
A First-Order Superscalar Processor Model
See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/3044068
Functional Implementation Techniques for CPU Cache Memories